1. Field of the Invention
The present invention generally relates to a reference ladder having improved feedback stability that can provide reference voltages for an analog-to-digital converters (ADC), and other types of circuits that utilize reference voltages.
2. Background Art
Analog-to-digital converters (ADCs) convert analog signals into a digital format for further efficient processing using digital circuits and/or processors. As digital control and processing are applied to more numerous applications, the demand for ADCs continues to increase. Furthermore, there is an increasing demand for ADCs that are inexpensive and that provide high performance.
A conventional ADC often includes a voltage reference ladder (also called a reference ladder) having a resistor ladder with a plurality of taps. Each tap provides a reference voltage that is utilized by the ADC to quantize the incoming analog signal. More specifically, a bank of ADC comparators (or differential input stages) compares the reference voltages from the reference ladder to the analog signal in order to quantize the analog signal and generate a digital output signal.
The accuracy of the analog-to-digital conversion is heavily dependent on the accuracy of the reference voltages from the reference ladder. More specifically, the ADC full scale range is controlled by these voltages. Accordingly, a feedback network is utilized to maintain the accuracy of the reference voltages. The feedback network utilizes certain taps of the reference ladder known conventionally as “sense” points or taps, and “force” points (or taps). A voltage or current source is applied at the force taps to control the reference voltages that are produced by the reference ladder. The force taps are usually the first and last taps on the reference ladder. The sense taps are certain taps on the reference ladder that are monitored (or sensed) to check if the desired reference voltages are being produced by the reference ladder. More specifically, an operational amplifier (op amp) compares the voltage across the sense taps with a desired reference voltage (e.g. ADC full scale voltage), and adjusts the voltage or current source at the force taps to produce the desired voltage across the sense taps.
A bank of ADC comparators are connected to the taps of the reference ladder and receive the reference voltages. The ADC comparators have associated circuit parasitics that load the sense taps. As a result, the parasitics of the ADC comparators effect the voltage and current at the sense taps, and effectively load the feedback control loop that drives the force taps of the reference ladder. Furthermore, since the sense taps are taken across a subset of the plurality of taps, a portion of the reference ladder resistance is also in the feedback control loop. Both the circuit parasitics and the reference ladder resistance contribute to de-stabilization of the feedback control loop.
Accordingly, it is desirable to configure the reference ladder so as to prevent the ADC comparators and the ladder resistance from loading the feedback control loop, so as to improve the loop stability.